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VLSI의 게이트레벨 論理故障 시뮬레이션에 關한 硏究 = A Study on Gate Level Logic Fault Simulation for the VLSI
VLSI의 게이트레벨 論理故障 시뮬레이션에 關한 硏究 = A Study on Gate Level Logic Fault Simulation for the VLSI
장경찬 韓陽大學 大學院, 1985,
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(A) transistor Level Logic Simulator for MOS LSI Circuits : MOSLOG
(A) transistor Level Logic Simulator for MOS LSI Circuits : MOSLOG
byung Ik,Kang Hanyang University Graduate School, 1986,
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